This invention relates to electrostatic discharge protection.
Electrostatic discharge (ESD) can damage integrated circuits (ICs). ESD is caused when a source of electrostatic potential (e.g., a human body with a static buildup of charge carriers) comes into contact with a circuit input. The electrostatic voltage may damage sensitive ICs if it discharges through circuit elements.
In order to prevent damage to functional circuits on the IC due to ESD, protective circuits may be incorporated on the input/output pads of the IC. Rather than discharging through functional circuit elements, electrostatic potential is discharged through the protective ESD device.
FIGS. 1A-1C show a protective circuit 100 with a lateral NPN device (referred to also as a gateless NMOS structure) including one or more fingers 105. Protective circuit 100 includes a base contact region 110 of p-type conductivity having one or more contacts 115. Generally, region 110 is more highly doped than a p-well region 160 in a substrate. Herein, the term xe2x80x9cmore highly dopedxe2x80x9d refers to a region with a net impurity concentration that is higher than the region to which it is being compared. Similarly, xe2x80x9cmore lightly dopedxe2x80x9d refers to a region with a net impurity concentration that is lower than the region to which it is being compared.
Circuit 100 includes one or more emitter regions 120 having one or more contacts 125, and one or more collector regions 140 having one or more contacts 145. Circuit 100 includes field oxide regions 130 between regions 120 and 140. Emitter regions 120, collector regions 140, and portions 165 of p-well region 160 (which act as base regions) form natural npn transistors. A field oxide region 150 separates region 110 from the fingers of the lateral NPN (also referred to as a gateless NMOS structure). In an implementation, emitter regions 120 may be coupled with one or more power sources, while collector regions 140 may be coupled with one or more pads.
In normal operation, the base is grounded. If there is an ESD event (e.g., a pad of the IC experiences an electrostatic potential), there is a reverse junction breakdown in the npn transistor. The electrostatic potential is initially discharged as current which flows from collector regions 140 to p+ region 110.
FIG. 1C shows a schematic of the natural npn transistor structures formed in circuit 100. A first resistance R1 exists between the base portion of the edge npn structure and region 110. A second resistance R2 exists between the base regions of adjacent npn structures.
When an ESD stress is applied to an input/output pad of the IC, the breakdown voltage of the appropriate pn junction is exceeded, the discharge current or pulse transient current is initially conducted out of the ESD structure from collector regions 140 to p+ region 110.
The structure shown in FIGS. 1A-1C may be modified. For example, the structure may be modified so that the npn transistor breaks down at a lower voltage. FIG. 1D shows a collector region 140 that may be used to lower the breakdown of an ESD structure. Collector region 140 may include p-pockets 170 beneath the outer portions of n+ collector regions 140. P-doping a region underneath the n+ region allows the ESD structure to break down at a lower voltage.
P-pockets 170 are generally formed using an xe2x80x9cESD implant;xe2x80x9d that is, an implant step in a pxe2x88x92 region is implanted under nxe2x88x92 regions, but in which the protected circuit is not implanted. This additional processing step may add cost and complexity to the fabrication of the IC.
In general, in one aspect, an integrated circuit may include an electrostatic discharge structure and a plurality of semiconductor structures to process data, such as one or more transistors. The electrostatic discharge structure may discharge an electrostatic voltage applied to a pad of the integrated circuit such as an input pad or an output pad. The electrostatic discharge structure may therefore reduce or prevent damage to the semiconductor structures.
In general, in another aspect, a collector region of an electrostatic discharge device may include a middle region of a first conductivity type, top side regions of the first conductivity type, and bottom side regions of a second conductivity type. The first conductivity type may be n-type and the second conductivity type may be p-type. In an implementation, the top side regions may be more lightly doped with n-type impurities, the bottom side regions may be p-pocket regions, and the middle region may be a highly doped with n-type impurities.
A process for forming such a collector region in an electrostatic discharge device may include forming a layer of a first conductivity type in a first process using a first mask. The method may further include forming a layer of a second conductivity type proximate to the layer of the first conductivity type in a second process using the first mask. The process may include forming the middle region using a second mask.
The process described above to form collector regions for an ESD device may be integrated with the formation of regions of the first and second conductivity types near gate electrodes of transistors included in the circuits to be protected by the ESD device. That is, the layer of the first conductivity type formed using the first mask may be accomplished as a region of the first conductivity type is formed proximate to gate electrodes in the circuit to be protected. Similarly, the layer of the second conductivity type formed using the first mask may be accomplished as a region of the second conductivity type is formed proximate to the gate electrodes.
The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims.